1. Field of the Invention
This invention relates to a method of controlling nonvolatile memory device, and more particularly to a method of electrically erasing data stored in nonvolatile memory elements or cells simultaneously with one another.
2. Description of the Prior Art
Flash memory, which is one of electrically rewrittenable nonvolatile memory devices (EEPROMs) permitting a set of memory elements thereof to be simultaneously electrically-erased, is disclosed in an article entitled "An in-system reprogrammable CMOS flash memory" Virgir Niles Kynett, etc., IEEE Journal of Solid-state Circuits, Vol. 23, No. 5, October 1988, pp. 1157-1163.
Similarly to EEPROM elements erasable individually, memory elements or memory cells of this flash memory device have a stacked-gate structure as shown in FIG. 1:
Formed in a p-type silicon substrate 1 are an n-type source region 7 and an n-type drain region 6. A first oxide insulating film 2 of about 10 nm in thick is formed over the channel region 8 between regions 6 and 7 to overlap slightly regions 6, 7 at their edges 9. On the first gate insulating film 2 floating gate electrode 3 of polycrystalline silicon 3 and a second gate insulating film 4 of 25 nm in thick are formed in that order. Further on this top surface a control gate electrode 5 is formed. The prior art memory cell of this type will be briefly set forth below.
Writing or storing data in memory cells is carried out by applying a voltage such as +7 V (drain voltage Vd) to drain region 6 while semiconductor substrate 1 and source region 7 are being connected to the ground potential (V.sub.sub =V.sub.s =0 V). Further application of voltage such as +12 V (V.sub.cg) is carried out to control gate electrode 5. Floating gate electrode 3 is completely electrically-isolated, and hence its potential is determined as one value by the ratio between the source/drain-floating gate capacitance and control gate-floating gate capacitance, together with by the potentials of control gate electrode, source/drain regions and semiconductor substrate. Usually if the potential of the floating gate is set to much the same as the drain potential, the maximum amount of hot electrons (those having energy overcome the barrier of the first gate insulating film) from current flowing between the source and drain regions, which are injected into the floating gate electrode, is available. Many times. The above-mentioned potentials are set. Under these conditions, electrons are injected into the floating gate and its potential is forced to drop to a negative level. Consequently the threshold voltage of the memory cell, or that with respect to control gate electrode, shifts in the positive direction to about +7 V set commonly.
Conversely, for erasing the data of the memory cell the above-mentioned injected electrons are forced to flow out of the floating gate. This is accomplished, for example, by connect the substrate and the control gate to the ground potential (V.sub.cg /V.sub.sub =0 V), and applying +12 V (V.sub.s) to the source in open state of drain region 6.
The potential of floating gate 3 depends on the potentials of the regions, as described above, and itself is at a negative potential when written. As the result that this negative potential adds, a fairly large electric field (1.0 MV/cm or more at those potentials) is applied to the first gate insulating film 2 between source region and floating gate 3, and as well-known, causes the quantummechanical Fowler-Nordheim tunneling current (referred to as FN current hereinafter) to flow across the first gate insulating film, as well-known. The memory cell can be erased by making use of this effect to flow of electrons from floating gate 3 to source region 7.
As stated above, "written" is defined as "state of the memory cell with its threshold voltage shifted in positive direction by injecting electrons into the floating gate" and "erased" as "that with its threshold voltage shifted in negative direction by removing electrons from the floating gate". These are not always considered as limiting but others by which two different states of the memory cell are represented may be of course used.
Writing and erasing of the memory cell are performed in such a way. For flash memory, writing is carried out by the above-mentioned method while it is possible to erase collectively a memory cell array consisting of a certain number of memory cells arranged in matrix by applying voltage V.sub.s simultaneously to all the source regions after connecting them to a common terminal. This enables to erase a large capacity memory in a shorten time.
There was however a problem for the conventional flash memory as described above that collectively erasing a memory cell array results in a too-wide-dispersed threshold voltages of the memory cells.
This is because that in the case of erasing simultaneously a plurality of memories the amount of electrons tunneling from floating gate electrode 3 to source region 7 or the FN current, which can be determined by various physical conditions: applied voltage, the thickness of the first gate insulating film 2, the area of floating gate 3 overlapping source region 7. These varies inevitably from memory cell to memory cell depending on fabrication process. This reflects the inevitably-varying FN current values, and correspondingly the amounts of electrons removed from floating gate 3 to source region 7 differ among memory cells with deviations of the extent of going beyond its permissible range.
FIG. 2 is a graph showing the distribution of the threshold voltages V.sub.th of a flash memory, which plots the results of measuring them after erasing. The graph shows a substantially normal distribution of which the width "Z" between the upper and lower limit values is about 2 V. In other words, erasing simultaneously all EEPROM memory cells of a memory array having some memory capacity such as 256 kbits (32 kbytes) results in a difference of about 2 V in threshold voltage V.sub.th between the earliest- and the latest-erased memory cells, and the distribution extends below 0 V. For erasing collectively the memory cell array of the flash memory device as mentioned above therefore it is necessary to interrupt the entire erasing operation before the threshold voltage of the memory cell which is being earliest erased goes down beyond 0 V because, as well known, for any memory cell connected to a bit line, drop of the threshold voltage to below-zero voltages could make it impossible to raise the potential of the bit line, with a result that both writing into and reading from all the memory cells become impossible.
If the entire erasing operation was interrupted before going down below 0 V, the latest-erased memory cell, as considered from the aforesaid distribution, inevitably would become higher than 2 V in threshold voltage. Practically it is common to set the erased-state threshold voltages of the memory cells to about 2.5 to about 3 V, estimating 0.5 to 1 V as room of threshold voltage of the earliest-erased memory cell. This makes it impossible to set the potential of the word line to any below the threshold voltage of the latest-erased memory cell, which means that in the prior art the write/readout voltages can not used if they are below 2.5 to 3.5 V. It however follows that flash memories only can not cope with application-voltage lowering in the technological fashion of lowering application voltages. For the purpose of overcoming this, effort have been devoted to reducing dispersion of erased-state threshold voltages of the memory cells by the use of various methods.
For reducing the unwantedly-wide dispersion of threshold voltages to a desired value it is needed to minimize variation in the above-mentioned physical parameters among memory elements but difficult because of obstacles to improvement of fabrication process.
In this circumference has been proposed a method for reducing dispersion of threshold voltage with an electronic procedure following collective erasing in an article entitled "A self-convergence erasing scheme for a simple stacked gate flash EEPROM" Seiji Yamada, IEDM, etc. 91, pp. 307-310, which will be described with reference to FIG. 3 and also to FIG. 1 as needed.
FIG. 3 shows dependence of gate current (Ig: current of flowing into or out of the floating gate) on positive floating-gate potential. When the source-drain voltage is greater than the floating gate potential, i.e. V.sub.sd &gt;V.sub.fg, hot carriers of the source-drain current are injected into floating gate 3 (generation of gate current). Then whether carriers injected are electrons or holes depends on the potential of floating gate 3. In FIG. 3 are seen three sections, in sequence of rising potential of floating gate 3 V.sub.fg, of channel electron-induced avalanche hot hole (CEIA-HH), channel electron-induced avalanche hot electron (CEIA-HE) injection, channel hot electron (CHE) injection. The potential represented by V.sub.fg * is a transition point at which no hot carrier injection occurs and CEIA-HHs and CEIA-HEs is in balance.
For example, under the conditions meeting V.sub.fg &gt;V.sub.fg * and V.sub.ds &gt;V.sub.fg, CEIA-HE injection into the floating gate 3 occurs, which lowers its potential, which in turn decreasing CEIA-HE injection. Thus, the potential eventually converges at V.sub.fg *.
An example in the prior art will be described with reference to FIG. 4 showing a timing diagram of the voltages of the electrodes during data erasing. With a drain voltage (V.sub.d) of 0 V, application of a control-gate voltage pulse (V.sub.cg) of -13 V and 0.1 sec, and a source voltage pulse (V.sub.s) of +0.5 V and 0.6 sec induces FN current and consequently electrons escape floating gate 3 during the first 0.1 sec, eventually its potential converges, and in turn the erased-state threshold voltage with respect to the control gate converges at a certain value. This contributes to reducing dispersion.
However, the above-mentioned data-erasing method for nonvolatile memory device utilizes avalanche phenomenon as means for reducing dispersion of the erased-state threshold voltages. This presents the problem of allowing the hot carrier injection associated with avalanche phenomena to damage the source and drain regions, resulting in lowered breakdown voltage of the junctions between these regions and the semiconductor substrate. The avalanche phenomenon further causes hot carrier injection into the overlapped area of the drain region and the gate insulating film, too, resulting in degradation of the gate insulating film.
In addition, this process of reducing the dispersion of the erased-state threshold voltages consumes large power needing for the hot electron injection current into the floating gate and additionally source-drain current for generation of avalanche phenomenon.